Intel DFx Design Engineer in Folsom, California
- If you're interested in computer graphics and working with leading graphics engineers on Intel's latest GPU/CPU architecture, then our Visual Technologies Team VTT has opportunities for you. In VTT, we are focused on delivering Best-in-Class visual experiences that enable users to immerse themselves in a new visual future.
As a member of the VTT Graphics Hardware DFx group, this position is responsible for the following activities:
Work on the design, RTL/GLS validation, automation, and/or timing analysis in one of the following DFx domains: Controller, Scan, Array DFT, Functional DFT, or DFD.
Contribute to trace/pattern generation efforts as well as post-silicon enabling, debug support, and/or analysis of the DFx features/content types.
*BS/MS in Electrical Engineering or related field with 2+ years working experience with SOME OR ALL of the following:
- Verification/Validation in RTL/GLS simulation/environment using industry standard simulator e.g. VCS/modelsim
- Logic Design using Verilog and/or System Verilog
- System Verilog Test Bench Design
- DFx features such as Controller, Scan, Array DFT, Functional DFT, or DFD.
- Programming/Scripting language(s) such as C/++/# and/or Perl.
*Preferred Experience & Skills
Knowledge/experience with post-silicon enabling/debug of the DFx features on the tester or system validation.
- Some exposure toStructural Design flows such as timing, routing, placement, or clocking analysis.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.
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